The WFC features two 2048 × 4096 pixel CCDs based on a commercial design manufactured by Scientific Imaging Technologies (SITe). The configuration of the ST008A chip, specifically designed for ACS, has the serial register along the 4096 pixel edge, to reduce the number of pixels which can be involved into a radiation damage event. This chip is designed to be buttable along only one edge making the 2×1 mosaic possible (see figure). Additional information on the commercial device ST002A are available at the SITE web page.
The imaging area consists of 4096 columns each of 2048 pixels. Each pixel is 15 micron × 15 micron in size. The serial register, located at the bottom along one of the 4096 pixel edges of the device, is split in the middle so that the entire device can be readout either one or both the amplifiers that terminate the serial register. There are 25 additional extended pixels (physical overscan) on each side of the serial readout register just before the A and B amplifier. The WFC data will contain also a virtual overscan, 20 rows on top of the chip, obtained clocking after the readout of the first CCD row. Once mosaicized the gap between the two CCDs is aproximatively 30 pixels, which correspond to a 1.5".
The WFC CCDs are three phases back-illuminated devices. Each chip, approximatively 6.88 × 3.46 cm2 in size, prior the thinnig process, is turned over and mounted to a thick ceramic header, to guarantee that the CCD will remain flat (see long wavelenght halo solution). The thinning process reduces the silicon thickness from 525 to 15 micron. Several treatments of the thinned CCD backside are needed to obtain the highest quantum efficiency (QE) backside passivation process and antireflection coating have been performed by SITe with ion implant and a VIS-AR coating which optimize the response of the WFC CCD in the I band. In order to reduce the dark current rate and minimize the ionizing radiation damage, the CCD will be operated in Multi Pinned Phase (MPP) mode. Moreover, in order to reduce the charge transfert efficiency (CTE) degradation due to radiation damage the design of the WFC CCDs incorporates a narrow (~3 micron) extra-doped channel inside the buried channel. The higher potential in this mini-channel allows to store and transfer small charge packets (~5-10 Ke-) reducing the interactions with traps in the buried channel, significatively improving the CTE at these low signal levels.
The WFC CCD package (fig) is a scaled up version of the STIS design with the addition of a second cooled window to reduce the radiative heat load (see an expanded view of the WFC CCD assembly). It consists on two major subassemblies: the front cover and the aft baseplate. The front cover holds a hermetically soldered MgF2 window and a single element optical baffle for the CCD detector. The aft baseplate (fig) holds the CCD, the TECs and a small printed wired board. The TEC is soldered to the aft baseplates. To increase the useful life of the CCD in orbit the assembly provides one cm of molybdenum radiation shielding with low secondary emission. It also provides a highly conductive thermal path to remove the heat from the TEC.